Several types of integrated circuit capacitors exist, which are classified according to their junction structures, such as metal-oxide-silicon (MOS) capacitors, pn junction capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and metal-insulator-metal (MIM) capacitors. In all of the above-listed capacitors except for MIM capacitors, at least one electrode is formed of monocrystalline silicon or polycrystalline silicon. However, physical characteristics of monocrystalline and polycrystalline silicon limit minimizing the amount of resistance of a capacitor electrode. In addition, when a bias voltage is applied to a monocrystalline or polycrystalline silicon electrode, depletion may occur, which can cause the applied voltage to become unstable. When this occurs, the capacitance of the silicon electrode cannot be maintained at a certain level.
Using MIM capacitors has been proposed to address the varying capacitance problem, since capacitance of MIM capacitors does not depend on a bias voltage or temperature. MIM capacitors have a lower voltage coefficient of capacitance (VCC) and a lower temperature coefficient of capacitance (TCC) than other capacitor types. The VCC indicates variation of capacitance according to the changes in voltage and the TCC indicates variation of capacitance according to the changes in temperature. Because of having a low VCC and TCC, MIM capacitors have been particularly useful for fabricating analog products. More recently, MIM capacitors have been used to make mixed mode signal products and system-on-a-chip (SOC) products. For example, MIM capacitors have been widely employed in analog capacitors and filters for analog or mixed mode signal applications in wired or wireless communications, as decoupling capacitors for main processing unit boards, as high frequency radio-frequency (RF) capacitors, and in embedded DRAMs.
FIGS. 1 and 2 are cross-sectional diagrams of two conventional MIM capacitors as taught by R. Liu et al., Proc. IITC, 111 (2000) and M. Armacost et al., Proc. IEDM, 157 (2000), respectively. Reference numerals 10 and 12 indicate MIM capacitors, and reference numerals 20, 30, 40, and 50 indicate a lower electrode, a dielectric layer, an upper electrode, and a capping layer, respectively. In addition, reference numerals C/P_20, C/P_40, C/H, D/D_20, D/D_40, and D/R indicate a lower electrode contact plug, an upper electrode contact plug, contact holes, a dual damascene wiring layer contacting a lower electrode, a dual damascene wiring layer contacting an upper electrode, and damascene regions, respectively. Other parts of the MIM capacitors 10 and 12 correspond to interlayer or other dielectric layers.
In the MIM capacitor 10 shown in FIG. 1, the lower electrode 20 is electrically connected to a wiring layer (not shown) by the lower electrode contact plug C/P_20 and the upper electrode 40 is electrically connected to another wiring layer (not shown) by the upper electrode contact plug C/P_40. The lower electrode contact plug C/P_20 and the upper electrode contact plug C/P_40 are formed in their respective contact holes C/H having a high aspect ratio but different depths. Specifically, the C/H for the C/P_20 runs deeper than the C/H for the C/P_40, because the C/P 20 contacts the lower electrode 20. When forming the contact hole C/H, it is difficult to precisely control an etching process so as to stop the etching of C/H at the top surface of the upper electrode 40 and at the top surface of the lower electrode 20 simultaneously. Therefore, the upper electrode 40 must be formed to have a predetermined thickness so that it can endure an excessive etching process. However, as the thickness of the upper electrode 40 increases, the dielectric layer 30 under the upper electrode 40 is more likely to be exposed to an excessive etching process for patterning the upper electrode 40, and thus the lower electrode 20 may be exposed due to the dielectric layer 30, which is etched away. Therefore, the dielectric layer 30 must also be formed to have a predetermined thickness so that it can endure an excessive etching process, and this results in a decrease in the capacitance of the entire capacitor 10.
In the MIM capacitor 12 shown in FIG. 2, the dual damascene wiring layer D/D_20 and the dual damascene wiring layer D/D_40 are electrically connected to the lower electrode 20 and the upper electrode 40, respectively. They are formed in their respective damascene regions D/R having a high aspect ratio but different depths. In order to obtain a sufficient margin for an etching process for forming the dual damascene region D/R, in which the dual damascene wiring layer D/D_40 is supposed to be formed, the thickness of the upper electrode 40 and the thickness of the dielectric layer 30 must be increased, which accompanies the decrease in the capacitance of the entire capacitor 12.
In addition, there is a high probability of having a bad electrical contact occur due to byproducts, like polymer, generated during the formation of the contact holes C/H and the damascene regions D/R because they have a high aspect ratio. In other words, the manufacturing process of conventional MIM capacitors results in many disadvantages including limiting the capacitance of a capacitor.
Embodiments of the invention address this and other limitations in the prior art.